1. Field of the Invention
The principles of the present invention generally relate to liquid crystal display (LCD) devices. More particularly, the principles of the present invention relate to a thin film transistor (TFT) substrate and a simplified method of fabricating the same.
2. Discussion of the Related Art
Generally, LCD devices display pictures by controlling light transmittance characteristics of liquid crystal material via selectively applied electric fields. To this end, LCD devices typically include an LCD panel and driving circuits for driving the LCD panel.
The LCD panel has a plurality of liquid crystal cells arranged in a matrix pattern and generally includes a TFT substrate and a color filter substrate bonded to and spaced apart from the TFT substrates, thereby defining a cell gap between the two substrates. Liquid crystal material is provided within the cell gap as are spacers for maintaining cell gap uniformity.
The TFT substrate includes gate lines, data lines crossing the gate lines to define pixel areas, switching devices (i.e., TFTs) at crossings of the gate and data lines, pixel electrodes formed within the pixel areas and connected to corresponding TFTs, and an alignment film over the pixel electrodes. Each of the gate and data lines include pad portions that are electrically connected to predetermined driving circuits. Accordingly, the gate and data lines receive scanning and pixel signals, respectively, from the driving circuits via corresponding pad portions. In response to scanning signals applied to the gate lines, corresponding TFTs switch pixel signals, transmitted by corresponding data lines, to corresponding pixel electrodes.
The color filter substrate includes a plurality of color filters individually aligned over corresponding pixel electrodes, a black matrix between adjacent color filters for reflecting external light, a common electrode for applying a reference voltage to a subsequently provided liquid crystal layer, and an alignment film over the common electrode.
After the aforementioned TFT array and color filter substrates are prepared, they are bonded together via a sealant material to form a cell gap, liquid crystal material is injected through an injection hole within the sealant material and into the cell gap to form the liquid crystal layer. Subsequently, the injection hole is sealed and fabrication of the LCD panel is complete.
The process used to fabricate the TFT array substrate described above is complicated and relatively expensive because it involves a number of semiconductor processing techniques that require a plurality of mask processes. It is generally known that a single mask process requires many sub-processes such as thin film deposition, cleaning, photolithography, etching, photo-resist stripping, inspection, etc. To reduce the complexity and cost associated with fabricating TFT array substrates, procedures have been developed to minimize the number of masking processes required. Accordingly, a four-mask process has been developed that removes the necessity of a mask process from a standard five-mask process.
FIG. 1 illustrates a plan view of a TFT array substrate of an LCD device, fabricated using a related art four-mask process. FIG. 2 illustrates a sectional view of the TFT array substrate taken along the I-I′ line shown in FIG. 1.
Referring to FIGS. 1 and 2, the TFT array substrate includes gate lines 2 and data lines 4 formed so as to cross each other on a lower substrate 42 to define a plurality of pixel areas, a gate insulating film 44 between the gate and data lines 2 and 4, a TFT 6 provided each crossing of the gate and data lines 2 and 4, and a pixel electrode 18 provided at each pixel area. The TFT array substrate further includes a storage capacitor 20 provided at a region where each pixel electrode 18 and a previous gate line 2 overlap, a gate pad 26 connected to each gate line 2, and a data pad 34 connected to each data line 4.
Each TFT 6 allows a pixel signal transmitted by a corresponding data line 4 to be charged and maintained within a corresponding pixel electrode 18 in response to a scanning signal transmitted by a corresponding gate line 2. To this end, each TFT 6 includes a gate electrode 8 connected to a corresponding gate line 2, a source electrode 10 connected to a corresponding data line 4, a drain electrode 12 connected to a corresponding pixel electrode 18, and an active layer 14 overlapping the gate electrode 8 and defining a channel between the source electrode 10 and the drain electrode 12.
The active layer 14 is overlapped by the source and drain electrodes 10 and 12 of each TFT 6, the data lines 4, as well as a lower data pad electrode 36 and a upper storage electrode 22. An ohmic contact layer 48 is formed on the active layer 14 and ohmically contacts the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 36, and the upper storage electrode 22.
Each pixel electrode 18 is connected to a drain electrode 12 of a corresponding TFT 6 via a first contact hole 16 formed through a passivation film 50. During operation, a potential difference is generated between the pixel electrode 18 and a common electrode supported by a color filter substrate (not shown). In the presence of an electric field generated by the potential difference, molecules within the liquid crystal material (which have a particular dielectric anisotropy), rotate to align themselves vertically between the TFT array and color filter substrates. The magnitude of the applied electric field determines the extent of rotation of the liquid crystal molecules. Accordingly, various gray scale levels of light emitted by a light source (not shown) may be transmitted by a pixel area by varying the magnitude of the applied electric field.
Each storage capacitor 20 associated with a pixel area includes a previous gate line 2, an upper storage electrode 22 overlapping with the previous gate line 2 and separated from the previous gate line 2 by the gate insulating film 44, the active layer 14, and the ohmic contact layer 48. A pixel electrode 18 is connected to the upper storage electrode 22 via a second contact hole 24 formed through the passivation film 50. Constructed as described above, the storage capacitor 20 allows pixel signals charged within the pixel electrode 18 to be uniformly maintained until a next pixel signal is charged at the pixel electrode 18.
Each gate line 2 is connected to a gate driver (not shown) via a corresponding gate pad 26. Accordingly, each gate pad 26 consists of a lower gate pad electrode 28 and an upper gate pad electrode 32. The lower gate pad electrode 28 is an extension of the gate line 2 and is connected to the upper gate pad electrode 32 via a third contact hole 30 formed through the gate insulating film 44 and the passivation film 50.
Each data line 4 is connected to a data driver (not shown) via a corresponding data pad 34. Accordingly, each data pad 34 consists of a lower data pad electrode 36 and an upper data pad electrode 40. The lower data pad electrode 36 is an extension of the data line 4 and is connected to the upper data pad electrode 40 via a fourth contact hole 38 formed through the passivation film 50.
Having described the TFT array substrate above, a method of fabricating the TFT array substrate according to the related art four-mask process will now be described in greater detail with reference to FIGS. 3A to 3D.
Referring to FIG. 3A, a gate metal pattern, including the gate line 2, the gate electrode 8, the lower gate pad electrode 28, is formed on the lower substrate 42 in a first mask process.
Specifically, a gate metal layer is formed over the entire surface of the lower substrate 42 via a deposition technique such as sputtering. The gate metal layer may have a single- or double-layered metal structure including chromium (Cr), molybdenum (Mo), an aluminum (Al) group metal, etc. After being deposited, the gate metal layer is patterned using photolithography and etching techniques in conjunction with a first mask pattern to provide the aforementioned gate metal pattern.
Referring next to FIG. 3B, a gate insulating film 44 is coated over the entire surface of the lower substrate 42 and on the gate metal pattern. In a second mask process, a semiconductor pattern and a data metal pattern are provided on the gate insulating film 44. The semiconductor pattern consists of the active layer 14 and the ohmic contact layer 48. The data metal pattern consists of the data line 4, the source electrode 10, the drain electrode 12, the lower data pad electrode 36, and the upper storage electrode 22.
Specifically, the gate insulating film 44, a first and a second semiconductor layer, and a data metal layer are sequentially formed over the surface of the lower substrate 42 and on the gate metal pattern by deposition techniques such as plasma enhanced chemical vapor deposition (PECVD) and sputtering. The gate insulating film 44 typically includes an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx). The active layer 14 is formed from the first semiconductor layer and typically includes undoped amorphous silicon. The ohmic contact layer 48 is formed from the second semiconductor layer and typically includes an n+ amorphous silicon layer. The data metal layer typically includes a material such as molybdenum (Mo), titanium (Ti), and tantalum (Ta).
After depositing the data metal layer, a photo-resist film (not shown) is formed and is photolithographically patterned using a second mask pattern. Specifically, the second mask pattern is provided as a diffractive exposure mask having a diffractive exposure region corresponding to a channel of a subsequently formed TFT. Upon exposure through the second mask pattern and development, a photo-resist pattern is created wherein a portion of the photo-resist film remaining in a region corresponding to the channel has a lower height relative to portions of the photo-resist film remaining in regions outside the channel.
Subsequently, the photo-resist pattern is used as a mask to pattern the data metal layer in a wet etching process, thereby forming the aforementioned data metal pattern, wherein the source and drain electrodes 10 and 12 are connected to each other in a region corresponding to the channel of the subsequently formed TFT 6. Next, the photo-resist pattern is used as a mask to sequentially pattern the first and second semiconductor layers in a dry etching process and form the aforementioned semiconductor pattern.
After the semiconductor pattern is formed, the portion of the photo-resist having the relatively lower height is removed from the region corresponding to the channel in an ashing process. Upon performing the ashing process, the relatively thicker portions of the photo-resist in regions outside the channel region are thinned but, nevertheless, remain. Using the remaining photo-resist pattern as a mask, the portion of the data metal layer and the ohmic contact layer 48 arranged in the channel region are then etched in a dry etching process. As a result, the active layer 14 within the channel region is exposed, the source electrode 10 is disconnected from the drain electrode 12, and the remaining photo-resist pattern is removed in a stripping process.
Referring next to FIG. 3C, the passivation film 50 is coated over the entire surface of the lower substrate 42, and on the gate insulting film 44, the data metal pattern, and the active layer 14. In a third mask process, the first to fourth contact holes 16, 24, 30, and 38, respectively, are formed.
Specifically, the passivation film 50 is formed over the surface of the lower substrate 42, and on the gate insulting film 44, the data metal pattern, and the active layer 14 via a deposition technique such as PECVD. The passivation film 50 typically includes an inorganic insulating material such as SiNx or SiOx, or an organic material having a small dielectric constant such as an acrylic organic compound, benzocyclobutene (BCB) or perfluorocyclobutane (PFCB). The passivation film 50 is then patterned via an overlaying third mask pattern using photolithography and etching processes to thereby define the first to fourth contact holes 16, 24, 30 and 38.
The first contact hole 16 is formed through the passivation film 50 to expose the drain electrode 12, the second contact hole 24 is formed through the passivation film 50 to expose the upper storage electrode 22, the third contact hole 30 is formed through the passivation film 50 and the gate insulating film 44 to expose the lower gate pad electrode 28, and the fourth contact hole 38 is formed through the passivation film 50 to expose the lower data pad electrode 36.
Referring next to FIG. 3D, a transparent conductive pattern including the pixel electrode 18, the upper gate pad electrode 32, and the upper data pad electrode 40 are formed on the passivation film 50 in a fourth mask process.
Specifically, a transparent conductive material is coated over the entire surface of the passivation film 50 and within the first to fourth contact holes 16, 24, 30, and 38 via a deposition technique such as sputtering. The transparent conductive material typically includes indium-tin-oxide (ITO), tin-oxide (TO), or indium-zinc-oxide (IZO). In a fourth mask process, the transparent conductive material is patterned using photolithographic and etching techniques using a fourth mask pattern to thereby form the aforementioned transparent conductive pattern.
Accordingly, the pixel electrode 18 is electrically connected to the drain electrode 12 via the first contact hole 16 while also being electrically connected to the upper storage electrode 22, via the second contact hole 24. The upper gate pad electrode 32 is electrically connected to the lower gate pad electrode 28 via the third contact hole 30 and the upper data pad electrode 40 is electrically connected to the lower data pad electrode 48 via the fourth contact hole 38.
While the TFT array substrate described above may be formed using a four-mask process that is advantageous over previously known five-mask processes, the four-mask process can still be undesirably complicated and, therefore, costly. Accordingly, it would be beneficial to fabricate a TFT array substrate according to a less complex, and therefore less costly, process.
Further, because the active and ohmic contact layers 14 and 48, respectively, are below the upper storage electrode 22, the distance between the upper storage electrode 22 and the aforementioned previous gate line 2 (functioning as a lower storage electrode) can become undesirably large. Because capacitance is inversely proportional to the distance between capacitor electrodes, the capacitance of the related art storage capacitor 20 can become undesirably reduced. To compensate for such a reduction, the area of overlap between the upper storage electrode 22 and the previous gate line 2 must be enlarged. This solution, however, is undesirable as an increase in overlap area between the upper storage electrode 22 and the previous gate line 2 results in a decrease in the aperture ratio of the pixel electrode 18.